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I'm currently trying to emulate ARMv4T and wasn't able to find any information about this: When and exception handler returns, it has to move the saved PC value (r14) to the PC register and set the status register to the saved status register. This has to be done in the same instruction, since restoring CPSR might change to thumb mode and could thus cause the setting of PC to be interpreted incorrectly. In the technical reference manual of the ARM7TDMI (the processor I want to emulate), it says that setting PC to the saved value will also automatically restore the status register (Example for undefined exceptions), but how does the processor know when that is done?

If it restores it whenever PC is set, that wouldn't allow for subroutine calls in exception handlers and comparing the value PC is set to with the expected value seems too inefficient to me.

Papierkorb2292
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    I don't remember if the same is true for v4, but for v5 I believe all/most data processing instructions will set `CPSR = SPSR` if the `S`-bit is set in the instruction and `Rd` is `PC`. See the "Operation" part for each instruction in document DDI 0100E. – Michael Jan 30 '23 at 14:47
  • confirmed, it is clearly documented in the arm arm as indicated in prior comment. – old_timer Jan 30 '23 at 16:48
  • Also, `LDM` with a ^ caret and PC. https://stackoverflow.com/questions/51341696/using-arm-ldm-instruction-to-transfer-data-into-user-mode-registers as well as ARM-TRM for the CPU version. – artless noise Jan 30 '23 at 19:58

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