Differences between CPU registers and RAM

Question

I've started to learn registers and assembly, but there are some ideas that are unclear and often mix. I have a few doubts (Assuming a 64bit computer):

1. What's the difference between the registers in the core of the CPU and the registers in ram? Meaning, as I understand it, in assembly for example the registers rax, rbx, rdx etc.. belong to the registers in CPU, and RAM is for storing a memory address with data in it, but isn't the CPU register the same (with less capacity)? Or is the register in CPU used only to access memory addresses in ram?

2. What's the difference between the two? does the register in cpu have the same structure as in ram (meaning: memory address and data for each one)?

3. Is the memory address 64 bits long and the data capacity for each address 8 bits in ram? Is so the same in a CPU register?

4. Is the register(rax, rbx,) being called constantly or usually by the CPU, even when we are not programming? for example if I open google chrome is the register(CPU) used for something, or is only the RAM used?

There has to be a process that is the one that constantly sends image to the screen, that's to say, that orders the pixels, or for example the one that tells the computer to keep running, to keep it "ON". Where are this process running? I ask these in particular because they should be constantly being called

Answer 1

As others are saying the CPU registers and memory are both capable of storing strings of bits.

The primary functional difference between CPU registers and memory is that memory supports indexing.

With memory, addresses are first class.  You may have heard the term first class being used with regard to functions: a programming language that has first-class functions can capture a reference to a function in a variable, such as a parameter, and hence supports passing functions as parameters.  It is significant that the function referred to by a function variable (say, a parameter) can be invoked.

Similarly, memory addresses can be stored in variables and passed as parameters, etc..   These variables are called pointers.  The memory referred to by a pointer can be accessed, and such access is called dereferencing, or a dereference.  A dereference can be either a read from- or a write to-memory operation.  Dereferencing is explicitly provided for by the hardware via its instruction set.  The mechanism for dereference varies among different instruction sets, though all go to the concept of addressing mode, which is the approach for computing an effective address of something of interest, given some initial pointer value, and instructing the processor to read or write.

So, memory can be indexed: take the address of something, pass as a variable or parameter, dereference such pointer variable to access values stored at that address. Because of this, memory can be used to store arrays, objects, and even code.

By contrast, for the majority of instruction set architectures, there are no special processor features (analogous to addressing modes for memory) for indexing registers, for taking the address of a register, for a pointer-like variable that refers to a register, for dereferencing a register pointer.

Support for register references on today's processors would require either a switch statement with one "case" per register, or, self-modifying code, or writing all the registers to memory (so we can use the indexing features of memory).  All of these would be rather inefficient (compared to using memory instead), so this generally isn't done.  (Though operating systems do the last for context switching, and, debuggers read (or write) that memory to report (modify) register values of processes stopped during debugging.)

Registers can only be named in instructions, so cannot be indexed; registers have names but not addresses; there is no built-in mechanism to manipulate a register reference, and hence, registers cannot really store arrays, objects, or code — but they are fast and directly accessible to machine code instructions.

Of course, the hardware inside a processor is an interpreter of machine code instructions, and as such, internally, is fully capable of using register numbers as references to the CPU registers.  But processors don't expose that feature to software except as what can be done by machine code instructions — which is to say machine code instructions identify the registers the program wants to use (each machine code instruction does this).  No matter what the computer is doing, the processor hardware is interpreting machine code instructions from some programming (modulo modern low power modes where the processor may simply be doing nothing).

There are also non-functional differences, in that the registers are limited in count and total amount of storage, while memory is practically unlimited. 

Since memory is addressed, the size of an address (in bits, sometimes called width, e.g. number of bits for a pointer variable, and number of bits used by dereference operations) determines how many different storage locations can be differentiated — hence this dictates the maximum size of memory.  So, using 32 bits for addressing limits storage to 4GB (2³²), and since that is sometimes not enough, we have processors with 64-bit support.

Further, modern CPUs are byte addressable, meaning that every byte (8-bits) of memory has its own unique address.  Variables of larger size than 8 bits (like 16-, 32- or 64-bits and larger) are often needed by programs — such a variable would necessarily occupy multiple bytes of memory — meaning also multiple addresses in memory.

Being byte addressable, in the context of needing more than one byte for certain data types, gives rise to two phenomena, one of which is scaling that is necessary in pointer arithmetic and the other is endian-ness for ordering of the bytes. 

A reference to a multi-byte memory item is done using one address, namely the numerically lowest address of its range.  Indexing into an array of 32-bit integers requires pointer arithmetic that scales the index by 4 since each such integer element takes 4 byte addresses (so index i is referred to as byte offset i*4).

Endian-ness is the property of exactly how the individual bytes of a multi-byte item are ordered in memory, since there are several possible orderings.  An instruction set architecture will make design choices that favor one of those orderings over the others.

Answer 2

They are both something that stores bits. And are both organized in a way to store a group of bits. But maybe think of the difference as individual pieces of paper vs a bound book. Now deep down in some processors the cpu registers are also bound like a tiny book with only 8 or 16 or 32 or so pages, where cache is a large book and main memory is a massively bound book. But at the end of the day it is paper you can print information on.

Like page numbers in a book each page has a unique address. So depending on the implementation of the cpu registers, maybe like cupholders in your car, you know where each one is and which person tends to use that one. So they are not necessarily addressed but hardcoded in certain locations in the logic. If you have a "register file" this is like the tiny 8 or 16 page book, those will way deep down have an address for each and the logic will have a map for r0 goes to address 0, r1 to address 1 and so on. Memory of course each location has a unique address.

Also understand that memory like the SRAM in cache is not organized in bytes usually it is organized in larger units like 32 bit or 64 bit or maybe there is parity (33 bits or 65) or ECC (40 bits or 72) in width then however deap so a byte based address of 0x123 (100100011) would going into a word based memory be at address 1001000 (0x18) in that memory block and be the first or last byte in that 32 bit location depending on endianness.

Because the cell library for a foundry will have a vast array of pre-built srams to choose from and they are optimized for size, it can make sense, if your design allows for it, to use these srams to implement processor cpu registers (a register file), and designers will do this when possible.

For CISC processors like the x86 you will often find them microcoded, meaning there is not straight logic that implements each instruction, instead there is a lower level processor sometimes something that resembles a RISC or VLIW, or it could just be muxes, alus and other with a control system (well a VLIW basically). So EAX may actually end up landing in some sram that the microengine operates on, there may be multiple copies of EAX at any one time depending on the pipeline and how that microengine works. So for microcoded processors like the X86, think of it as being an instruction set simulator using some other processor, only it is heavily optimized and hard coded for that high level (language) instruction set. And it operates at real-time.

Answer 3

Register is small and more faster memory inside CPU. It allows faster access of certain variables or data.It holds data temporarily while the main memory is a storage component in the computer that stores data and programs currently used by the CPU.