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I'm reading the intel manual, and I see mentions of "Linear Address Space of the processor".

I'm confused as to where or what the linear address space actually is. Where in the processor is the linear address space?

The Physical Address Space is the actual RAM as I understand. A logical address is a "segment selector" + "offset", and it must be translated to a physical address. If I understand, if paging is not used, the linear address space is effectively the same as a physical address in execution. And I read that every process can have it's own linear address. So if paging is used multiple processes that are in RAM simultaneously can each have their own linear address space with paging.

But I still don't know what the linear address actually IS, or where it is. Is the linear address space, the addresses in an executable file?

Peter Cordes
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    I don't know what you mean by "where". It's not a place, it's a concept. – Nate Eldredge Jun 25 '20 at 23:26
  • By where I meant how it is defined by the processor. Like the page tables for pages, and segment descriptors for segments. How does the processor define "linear address space" I know it doesn't need to represent a physical place in RAM. I see a lot of statements in the manual similar to this: "When a program attempts To ACCESS an ADDRESS LOCATION IN THE linear address space, the processor uses ... to translate the linear address into a physical address and then performs the requested operation on the memory location." "The LOCATION of the first byte of the segment IN THE linear address space" –  Jun 26 '20 at 03:38
  • Linear addresses are located in the linear address space, but the linear address space isn't located anywhere. – Ross Ridge Jun 26 '20 at 05:44

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Linear addresses are one step in the translation from seg:off as part of an addressing mode to eventually a physical address. You can't use them directly.

Windows runs with paging enabled, so linear address space = the virtual address space of the current process. Address decoding goes seg:off => linear, then virtual => physical. (More details)

This is why segmentation can't let 32-bit code access more than 4GiB of address space in a single process. (Which also makes sense if you keep in mind that page tables would have to be larger or deeper to translate more virtual bits to physical)

Windows (like very other mainstream x86 OS) uses a flat memory model so the only time the segment base is non-zero is with a segment override for thread-local storage, like mov rax, [gs: 0]. The offset part is 0, but the GS base will be different for every thread in the same process that shares the same linear virtual address space.

If you're not talking about normal Windows executables, e.g. a DOS program running in a virtual-8086 environment, then its seg:off addresses will translate to linear and get used directly as guest-physical addresses, inside the emulated or virtualized guest machine.

You can also do unusual stuff like run 16-bit protected mode processes, in which case linear address space is wider (32-bit I think) than the 16-bit offset part of an addressing mode. In this case non-zero segment bases might well be used if you wanted to address more than 64k of total address space.

Peter Cordes
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    Note that you can run 16 bit protected mode executables as well as real mode executables on some versions of Windows. In those cases, the segment base is frequently not zero. Additionally, nothing stops you from modifying the LDT. – fuz Jun 26 '20 at 00:13
  • @fuz: Fair enough, that's maybe a useful way to show what how linear addresses work in other cases than the simple base case of a native Windows 32-bit or 64-bit executable. IDK if that overcomplicates the explanation or helps, though. – Peter Cordes Jun 26 '20 at 01:04
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Linear addressing space is actually your physical memory space, when paging is not enabled in X86 processors.

But when paging is done, I think of the linear address space as an address of the memory location that can be addressed by the address bus.

But, This is not an actual Physical memory location in RAM (cause Paging is enabled) and a 2-level page translation is required to locate the memory location in the page frame of the Physical memory space.

Robert Houghton
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Venkat Raman
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    With paging enabled, you won't see linear addresses on any external bus. Your 2nd sentence sounds very weird to me. It's one step of translation inside a load or store execution unit. – Peter Cordes Dec 31 '21 at 21:05