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I have to implement a counter in VHDL and I realized I do not know the answer to a very simple question.

Suppose we have a signal x that is written in a process, and read at the same time in another one (i.e. it is assigned to another signal out):

process(clk, x)
begin
    if rising_edge(clk) then
        x <= x + 1;
    end if;
end process;

process(clk, x)
begin
    if rising_edge(clk) then
        out <= x;
    end if;
end process;

Both assignments seem to happen at the same time since they are conditional on rising_edge(clk). So will x be assigned to out after or before it is incremented? Or something in between resulting in undefined behaviour?

Cheers

Scrashdown
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    https://stackoverflow.com/questions/13954193/is-process-in-vhdl-reentrant/13956532#13956532 –  Feb 17 '20 at 17:00
  • Thank you for your reply. So if I understand well, a rising edge of the clock will schedule both processes (as per their sensitivity list) and both changes `x <= x+1` and `out <= x` will be stored to be executed later. However, when you say "Throughout this process, all signals have the value they originally had when the process woke up, and any signal assignments are stored up, to happen later", does this mean the right side value is computed when they wake up and assigned later? – Scrashdown Feb 17 '20 at 18:13
  • Yes, so `out` unambiguously sees the original value of `x`. Now if the second process was clocked one delta cycle later, it would see `x+1`. –  Feb 17 '20 at 18:20
  • `out` is a reserved word and cannot be used as a name or designator. Processes communicate by signals and suspend and resume in wait statements. A process sensitivity implies a wait statement waiting on the sensitivity list as the last statement. Signal updates are scheduled in a queue (a projected output waveform) and [occur in a different part of the simulation cycle](https://stackoverflow.com/questions/50158190/sequential-execution-in-process-statement-in-vhdl/50163596#50163596) than process execution. –  Feb 17 '20 at 22:25
  • @BrianDrummond I see, but in this case, could the 2nd process actually be clocked one delta cycle later? – Scrashdown Feb 17 '20 at 23:01
  • `clk2 <= clk; -- 1 delta cycle delay` ... and run process 2 off clk2. So ... don't do that. (Clock skews do pose problems ... but with synchronous design, inside an FPGA, the tools usually handle that for you. –  Feb 17 '20 at 23:03
  • I see, yes I don't see why I would want to do that. Thank you very much for the explanation. – Scrashdown Feb 18 '20 at 10:16

0 Answers0