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I'm newbie in ASIC design. I have a design with for example two inputs a ,b. I'm using the following code for initialize these two signals. But the Design compiler generating a warning that the register "a" is a constant and will be removed. When I'm trying to do post-synthesis simulation these two signals are all 'z'. So how can I apply initial signal assignment to avoid such a problem?

always @(posedge(clk) or posedge (rst)) begin
 if (rst) begin
     a<=4d'5;
     b  <=4'd10;
  end
end
user214497
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1 Answers1

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While describing hardware system, you need to consider that input signals to your module comes from another module/system and their values are decided by that signals. Inputs to any module can only be wire type.

You can think of a module as a box that has inputs and outputs. The values of output signals are decided by input signal + logic inside the box. However, the module cannot decide what its inputs should be. It is only possible if there is feedback, and even in that case it would depend on other signals that are outside of the module's control.

As a result, output signals can be declared as output reg but the same is not true for inputs. However there is solution to your problem, I think what you want can be designed using the following method:

module your_module(
input clk,
input rst,
//other inputs and outputs that you might need
input [3:0] a,
input [3:0] b
);
//define registers 
reg [3:0] a_register;
reg [3:0] b_register;
/* 
These registers are defined to make it possible to
to give any value to that logics when posedge rst 
is detected, otherwise you can use them as your
input logics
*/ 
//use initial block if you need
always@(posedge clk or posedge rst) begin
  if(rst) begin
    a_register <= 4'd5;
    b_register <= 4'd10;
  end
  else
    begin
      a_register <= a;
      b_register <= b;
      // and use a_register and b_register as you want to use a and b
    end
end
endmodule
Adhamzhon Shukurov
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  • Thank you for the response. But I don't want to define a and b as input ports. because they are originally two dimensional 40*64 arrays. I just want to [locally in the design by defining the registers] give them an initial value. I mean that I don't have option "else begin ". When I compile it with design compiler warning "The register is a constant and will be removed" will be pop up. – user214497 Feb 23 '19 at 13:11
  • Then you can initialize each row of them individually or you can use 'readmemb' or 'readmemh' – Adhamzhon Shukurov Feb 24 '19 at 03:22
  • Not sure about what kind of synthesizer you use, but if you think logically it should be possible. Most FPGA synthesis tools can do it. Check https://stackoverflow.com/questions/4321067/is-readmem-synthesizable-in-verilog – Adhamzhon Shukurov Feb 25 '19 at 08:30