1

Reading ARM Generic Interrupt Controller section 4.1.4, it has an explanation below:

Register banking refers to providing multiple copies of a register at the same address. The properties of a register access determine which copy of the register is addressed.

I'm a bit confused about at the same address. e.g. If R12 and R12_fiq are the same register, how would the processor guarantee the original data in R12 won't be overridden in fiq mode. And is there a need to guarantee that?

I am searching for a long time on net. But no use. All the related questions doesn't help me.

I think Benoit's answer in What does 'bank'ing a register mean? is kind of help, but I'm not sure.

Thanks in advance.

------------ updated-----

Due to domen's answer, R8_usr and R8_fiq are two different registers. Sorry that I don't know how to vote him. And I also notice that in ensc's answer word 'dedicated' is mentioned, maybe he knows they are different. But due to my poor description, he doesn't emphasize that.

Ynjxsjmh
  • 28,441
  • 6
  • 34
  • 52
  • GIC banking is for secure/normal world (or the NS bit of CP15). If you don't use trustzone, it does not apply. For the ARM modes (R8_FIQ, LR_IRQ, etc), the regular arm instructions that operate on the registers affect the banked register of the mode. GIC banking is different as it is at a memory mapped register address. Special context switch instructions which can access the banked registers from privileged modes. It lets the same code run in different modes without having to save registers; or in other cases it gives some way to save/restore the non-banked/shared registers. – artless noise Oct 17 '18 at 19:23
  • See many [Q/A on ARM banked registers](https://stackoverflow.com/search?q=%5Barm%5D+banked) here at stackoverflow. – artless noise Oct 17 '18 at 19:28
  • @artlessnoise Actually I'm not familiar with GIC, I just referred that from enjoylife's answer in link https://stackoverflow.com/questions/13432297/what-does-banking-a-register-mean. | I mentioned in my problem statement that I have read through the related questions which are familiar with your given link. | Anyway, thanks for your clear explanation for GIC banking. – Ynjxsjmh Oct 18 '18 at 02:38
  • It is just that *GIC banking* might have the same name, but it is functionally quite different from the *ARM registers banking*. It is conceptually the same. I just want to make sure that people looking at the question need to know one does not map 100% to the other (as well as help you understand). – artless noise Oct 22 '18 at 16:30

1 Answers1

1

"GIC" and R12 do not have many in common. GIC is a controller (used by some, but not every ARM CPU) which can be accessed by memory addresses. Depending on security mode and/or cpu node, the same address can provide a view to a different internal register.

R12 is a CPU register. Due to efficiency reasons (e.g. to avoid restoring its previous value when leaving FIQ), FIQ mode has a dedicated bank of the upper registers (r8-r15).

The stackpointer (r13) and lr (r14) can be banked too, so that e.g. IRQ mode can have its own stack or to signal certain states in lr (e.g. stack alignment).

ensc
  • 6,704
  • 14
  • 22
  • Sorry for my poor description, actually the reference part is from enjoylife's answer in . In your second paragraph, you mentioned that `FIQ mode has a dedicated bank of the upper registers (r8-r15)`. I guess you want to say r8_fiq to r15_fiq. And I notice the word `dedicated`, do you mean r8_fiq is differnt from r8_usr? For third paragraph, I have read this in the book 'ARM Architecture Reference Manual' section 2.3. – Ynjxsjmh Oct 16 '18 at 16:29
  • What I'm confused about is enjoylife's reference: > Register banking refers to providing multiple copies of a register at the same address. If this is true in ARM, I think r8_riq is the same with r8_usr despite the fact that r8_fiq can be only accessed in fiq mode. In fiq mode, I think processor can only accesse r8_fiq(I want to emphasize that it couldn't access r8_usr and etc.). If the processor changed the data in r8_fiq, will the data in r8_usr be changed too? If the r8_usr and r8_fiq is the same, I think it will be changed too. How do you think that? – Ynjxsjmh Oct 16 '18 at 16:31
  • sorry, it seems that breakline doesn't work and I don't know how to repair that. – Ynjxsjmh Oct 16 '18 at 16:35
  • 1
    you can not access `r8_fiq` directly. When you do `mov r8, #0` in FIQ mode, you write `#0` in `r8_fiq`; when you do this in ianother mode, you write into `r8_usr`. – ensc Oct 16 '18 at 16:47
  • I think I'd better spilt the problem into small pieces. (1) Do you agree with the sentence `Register banking refers to providing multiple copies of a register at the same address.`? (2) I agree with that sentence, I want to know according to `at the same address`, does it mean R8_usr and R8_fiq are the same register just be named different in two different modes? (3) If you don't agree with that sentence, do you think R8_usr and R8_fiq are the different register like the difference between R1 and R5? (4) More questions will be asked due to your answer. (5) Thanks in advance. – Ynjxsjmh Oct 17 '18 at 00:05
  • They are different registers, but are both accessible by same name, `R8`. Which one is selected depends on the mode the CPU is in. | (1) No, weird sentence. (2) No, you have it the wrong way around. (3) Yes. – domen Oct 17 '18 at 07:57
  • @domen Thanks for your reply, I understand now. In the link https://stackoverflow.com/questions/42810627/arm-banked-register, artless noise said that sentence is kind of right and he pointed out how to understand the meaning of 'address' in that reference. – Ynjxsjmh Oct 17 '18 at 10:17