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I am confused about Memory Map and Memory mapped I/O. Do general purpose registers, for example in ARM Architecture r0, r1, etc., are generally memory mapped?

Peter Cordes
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Jisung Kim
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  • Memory mapped registers are common on the ARM platform as they related to devices. On the x86, there is a notion of programmable I/O. It originally had two types of buses (and still does?). Compare [Von Neumann](https://en.wikipedia.org/wiki/Von_Neumann_architecture) vs [Harvard](https://en.wikipedia.org/wiki/Harvard_architecture). Conceptually, you can have a third bus for I/O versus program memory (be it instruction or data). You need CPU instructions that will use the alternate buses. ARM also has 'co-processor' instructions with `mcr` and `mrc` which some peripherals/devices use. – artless noise Sep 13 '18 at 14:40

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No, those registers are inside the actual CPU (or CPU core for multi-core CPUs). You can not access them through loads or stores to any memory address.

A memory-mapped register is something which you access through an address or a pointer (in languages that have pointers). I/O devices often have memory-mapped registers, where you write to or read from a specific address to set or get information or data. In other words, they are accessed just like any other memory (e.g. RAM).

As mentioned in comments, there do exist CPUs with memory-mapped CPU registers. They were almost all designed in the 1970's and are part of history now. The chances you would encounter a mainstream CPU (not microcontroller) with memory-mapped registers these days are slim to none.

Some microcontroller architectures do still use memory-mapped registers, including old designs like 8051, and even some more recent designs like PIC microcontrolers and AVR (an 8-bit RISC with thirty-two 8-bit registers). AVR MCUs come with at least 128 bytes of internal SRAM, the low 32 of which is also the register file.

Specifically for ARM, the ARM architecture does not have memory-mapped CPU registers. Peripherals, including those on the same SoC as the CPU's, are a different matter though: I/O registers are not at all the same thing because they're not also accessible via register-numbers as operands for instructions other than load or store. (And aren't even inside the core running your instructions.)

Peter Cordes
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Some programmer dude
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    I agree with this answer. In my experience of dozens of CPU architectures, memory mapped registers are very uncommon. The [PDP-11](https://en.wikipedia.org/wiki/PDP-11) has them and so does the [TI-9900](https://en.wikipedia.org/wiki/Texas_Instruments_TMS9900) but no others come to mind. Note that those two architectures are from the 1970s. – wallyk Sep 13 '18 at 07:06
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    Also the 8-bit PIC devices, which have so little RAM that typically all of the RAM is seen as registers from a programmer's perspective. But this lack of a clear distinction between registers and RAM is very rare. – cooperised Sep 13 '18 at 09:56
  • there have been and are processors where the general purpose processors are memory mapped yes. The arm is not one of those. So we can see the OP's confusion. – old_timer Sep 13 '18 at 21:31
  • the 8051 might as well, dont think it was AVR, so probably it was 8051 but would have to check...and yes I would expect this kind of feature to be something from that era at least for general purpose processors... – old_timer Sep 13 '18 at 21:32
  • @old_timer True, the only register not being memory-mapped on 8051 was the PC. And it had a lot of other quirks common of that early micro-processor era. – Some programmer dude Sep 14 '18 at 03:34
  • @wallyk: AVR (8-bit RISC microcontroller) has memory-mapped GPRs. [How do I directly access a memory mapped register of AVR with C](https://arduino.stackexchange.com/q/56304) has a map of memory address space (including the 32 GPRs in the low 32 bytes), and the I/O address space that overlaps that. – Peter Cordes Aug 30 '20 at 02:08
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    Mitch Alsup's My 66000 maps the registers to memory addresses. While there is no hardware implementation, the ISA design is modern. (I think the ISA is still pre-1.0.) –  Nov 26 '21 at 14:27
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    Actually, for My 66000 the thread context is memory mapped, but this does allow software to write into registers from another thread. I am not certain if the synchronization aspect has been fully defined yet (particularly for a thread writing its own registers), but as I understand it a running thread can have its register state updated from an external source. –  Nov 26 '21 at 18:33