how to concatenate a row buffer into a register in Verilog

Question

I have a problem with this

wire [7:0] table [0:999];
wire [8*1000-1:0] y;

assign y = {table[0], table[1], table[2], ...., table[999]}; // this line code is right, I don't want hard code

I want y is all 1000 values of table but I don't know how to assign all values in 1 line of code( or 2,3). code assign above is right but if there is 100000 values, do I have to type 100000 times?

yeah. I know. Do you know the faster way? I don't want to type 1000 times, — John T, Feb 16 '18 at 12:02

Oldfart · Accepted Answer · 2018-02-16T20:04:06.503

1

You can use a for loop but your problem is the sensitivity list. Not all simulators allow two dimensional arrays as sensitivity argument.

wire [7:0] tbl [0:999];
reg  [8*1000-1:0] y; // <<== Needs to be reg 

integer i;

always @( tbl ) // <<== may give error/warning
    for (i=0; i<1000; i=i+1)
        y[i*8 +: 8] = tbl[i];

edited Feb 16 '18 at 20:04

answered Feb 16 '18 at 12:03

Oldfart

6,104
2
13
15

Nope `[i*8+8-1:i*8]` is illegal unless `i` is a genvar. Also `++` is not supported in Verilog (it is in SystemVerilog) – Greg Feb 16 '18 at 19:51
Yes, I was writing some C code. Also y must be reg and 'table' is a reserved word. The above passed my Verilog syntax checker. – Oldfart Feb 16 '18 at 20:05
@Greg there is no genblock around, why genvar then? `+:` might not work though in verilog. – Serge Feb 16 '18 at 20:38
@oldfart Generate was added in Verilog-2001; so was `+:`/`-:`. A generate solution would look like: `genvar i; generate for(i=0;i<1000;i=i+1) begin assign y[i*8+8-1:i*8] = table[i]; end endgenerate` It works, but I find the `+:` is usually a cleaner. – Greg Feb 16 '18 at 20:46

score 1 · Answer 2 · answered Feb 16 '18 at 20:40

As long as you are using Verilog-2001 or higher, you can use:

wire [7:0] table [0:999];
reg [8*1000-1:0] y;
integer i;
always @* begin
  for (i=0; i<1000; i=i+1) begin
    y[ i*8 +: 8] = table[i];
  end
end

See: Indexing vectors and arrays with +:

Verilog-95 solution is not as pretty and has more overhead:

wire [7:0] table [0:999];
reg [8*1000-1:0] y;
integer i;
always @( table ) begin
  y = {8000{1'b0}};
  for (i=999; i>=0; i=i-1) begin
    y = {[8*999-1:0],table[i]};
  end
end

If you can use SystemVerilog, it can be done in one step with bitsteaming

wire [7:0] table [1000];
wire [8*1000-1:0] y = {<<8{table}};

how to concatenate a row buffer into a register in Verilog

2 Answers2