Verilog (assign in always)

Question

I came to know that we can use assign statements in procedural blocks(like in always), what will be the difference in using "assign" inside always block and outside it(in concern with synthesized circuit). I mean when it is absolutely necessary to use assign in always?

Answer 1

Never, assign keyword is for continuous assignment and it will generate combinatorial logic at synthesis. In fact, you can obtain the assign behaviour with an always block:

wire test;
//At all times, test equals input
assign test = input;

Is equivalent to:

reg test;
//Each time input changes(with the always@*), test takes its value
always@*
  test = input;

In always blocks, you should only use non-blocking assignment('<=') which are procedural assignments. Using blocking assignment is possible, however, you have to be sure to do what you want.

From this thread:

Two rules to live by that I know of no exceptions:

1. Always use blocking assignments for combinatorial or level-sensitive code, as well a clock assignments

2. Always use non-blocking assignments for variables that are written on a clock edge, and read on the same clock edge in another process.

Answer 2

assign and corresponding deassign (in always blocks) are also called 'procedural continuous assighment' can be used in always blocks for specific purposes. In most cases this is non-synthesizable and I had never ran across its use.

an example:

   reg in1, in2, out;
   reg [1:0] select;

   always @* begin
      case (select)
        2'b01: assign out = in1;
        2'b10: assign out = in2;
        2'b11: deassign out;
      endcase // case (select)
   end

general recommendateion -- do not use it.