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I was recently posed with this question. I am studying the ARM architecture, and I have tried researching it, but I feel like I do not got the right answer.

My idea is that the key reason is that to avoid messing with the ongoing interrupts, we use the set-enable registers for enabling all interrupts and the clear-enable registers for disabling all interrupts.

Is that the correct reason? Is there a deeper explanation behind it? Is there some document explaining this design decision?

EDIT: Sorry, the chip I'm working with is the Cortex M4

fgblomqvist
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  • Which registers, and furthermore, which architecture? As far as the A-class/legacy architecture is concerned, there are only two _bits_ in one register (one for disabling each type of interrupt), that's it. The M-class architecture is a bit different, and encompasses the actual interrupt controller itself as well, but it's still essentially just PRIMASK there. Or is there some confusion at play here between controlling whether the CPU _takes_ interrupts, vs. whether they are _generated_ in the first place? – Notlikethat Nov 23 '15 at 17:47

1 Answers1

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While I can't speak to the thoughts that went into the original design, my observation is that this makes it easier to ensure thread safety.

Assume there was just one register available to enable and disable interrupts; Setting a bit in the register would enable the corresponding interrupt, while clearing the bit would disable it.

This would be a read-modify-write operation, prone to race conditions unless the software carefully guarded against it (for instance, by disabling all interrupts before accessing the register, or by using a synchronization primitive).

Contrast this with separate set/clear registers, which do not require software synchronization at all. Any thread can set or clear individual bits without interfering with others.

Separate set/clear registers are also commonly used for e.g. GPIO, to allow multiple threads to freely modify I/O state.

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Carsten Hansen
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