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According to the ARM manual, it should be possible to access the banked registers for a specific CPU mode as, for instance, "r13_svc". When I try to do this gcc yells at me with the following error:

immediate expression requires a # prefix -- `mov r2,sp_svc'

What's wrong?

Update. The following text from the ARM Architecture Reference Manual for ARMv5 and ARMv6 led me to believe that it is possible, section A2.4.2:

Registers R13 and R14 have six banked physical registers each. One is used in User and System modes, and each of the remaining five is used in one of the five exception modes. Where it is necessary to be specific about which version is being referred to, you use names of the form: R13_mode R14_mode where mode is the appropriate one of usr, svc (for Supervisor mode), abt, und, irq and fiq.

Demiurg
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3 Answers3

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The correct syntax for this is mrs r2,sp_svc or mrs r3, sp_usr. This is a new armv7 extension. The code can be seen in the ARM Linux KVM source file interrupt_head.S. The gas binutils patch for this instruction support by Matthew Gretton-Dann. It requires the virtualization extensions are far as I understand.

According to what I understand, the LPAE (large physical address extension) implies the virtualization extensions. So Cortex-A7, Cortex-A12, Cortex-A15, and Cortex-A17 may be able to use this extension. However, the Cortex-A5, Cortex-A8, and Cortex-A9 can not.

Documentation on the instruction can be found in the ARMv7a TRM revC, under section B9.3.9 MRS (Banked register).

For other Cortex-A (and ARMv6) CPU's you can use the cps instruction to switch modes and transfer the banked register to an un-banked register (R0-R7) and then switch back. The obvious difficulty is with user mode. The correct way to handle this is with ldm rN, {sp,lr}^; user mode has no simple way back to the privileged modes.

For all older CPUs, the information given by old_timer will work. Mainly, use mrs/msr to change modes. mrs/msr works over the full class of ARM cpus but requires multiple instructions and hence may have race issues which require interrupt and exception masking depending on context.

This is an important instruction (sequences) for context switching (which VMs do a lot of).

artless noise
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  • Newer binutils give the error *Error: Banked registers are not available with this architecture.* when you try the instruction with compiler/assembler CPU flags that don't support the LPAE. – artless noise Jul 11 '14 at 22:05
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I don't think that's possible with the mov instruction; at least according to the ARM Architecture Reference Manual I'm reading. What document do you have? There are is a variant of ldm that can load user mode registers from a privileged mode (using ^). Your only other option is to switch to SVC mode, do mov r2, sp, and then switch back to whatever other mode you were using.

The error you're getting is because it doesn't understand sp_svc, so it thinks you're trying to do an immediate mov, which would look like:

mov r2, #0x14

So that's why it says "requires a # prefix".

Carl Norum
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  • I understand that. Please see the update above regarding the text from the ARM Architecture Reference Manual – Demiurg May 07 '10 at 08:25
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    @Demiurg, that paragraph is not referring to writing code, only to the conventions of the document. Since the banked registers are different, they have to have unique names so everyone isn't confused. It's not trying to imply that you could use those names in your assembly code. The instruction reference and addressing modes section later in the book are clearer about what you can and cannot do. – Carl Norum May 07 '10 at 15:13
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You use mrs and msr to change modes by changing bits in the cpsr then use r13 normally.

From the arm arm

MRS R0,CPSR
BIC R0,R0,#0x1F
ORR R0,R0,#0x13
MSR CPSR_c,R0

then

mov sp,#0x10000000

or if you need more bits in the immediate

ldr sp,=0x12345600

or if you dont want the assembler placing your data, you can place it yourself.

ldr sp,svc_stack
b 1f
svc_stack: .word 0x12345600
1:

You will see typical arm startup code, where the application is going to support interrupts, aborts and other exceptions, to set all of your stack pointers that you are going to need, change mode, set sp, change mode, set sp, change mode ...

old_timer
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  • If you look at the instruction encoding for a mov, there are four bits for the destination register, just enough for the 0xD (r13 or sp). There are 6 different sp registers you need 3 more bits in the instruction if you could specify the mode, I dont see those bits there so there is no way you can specify the mode in the instruction you have to change the cpsr using the cpsr modification instruction (msr). Note the different assemblers (arm, gcc, etc) use different syntax for msr/mrs and the mrc/mcr instructions. So arm arm syntax is likely for arm not gcc. – old_timer May 07 '10 at 02:48
  • Thanks. The code that you posted would probably do the trick. What led me to believe that it is possible to access these registers directly is the following text: Registers R13 and R14 have six banked physical registers each... Where it is necessary to be specific about which version is being referred to, you use names of the form: R13_ R14_ where is the appropriate one of usr, svc (for Supervisor mode), abt, und, irq and fiq. From the ARM Architecture Reference Manual. – Demiurg May 07 '10 at 08:21
  • Hmm, it is a very confusing section in the arm arm, I dont understand what they are implying. Perhaps their assembler adds instruction for you, except for perhaps Keil evals I dont have access to arm tools anymore. that section implies something special about armv6 related to the register banking and goes on to show what I showed above starting with "In archtecture versions prior to armv6". If r13_svc, r13_sys, etc were available on any instruction as this implies then every instruction would need space in its encodeing and a note in the encoding about if armv6 then... – old_timer May 07 '10 at 13:37
  • ran out of characters on that comment...I too am confused, the old fashioned way will (always?) work by switching modes with msr then use r13 and r14 directly. Unless you have a performance reason (rev, sxtab, for example) I find it easier to use code that ports to all architecture versions (when writing assembler). Well I assume armv4t and above I guess since bx lr is more portable than mov pc,lr for what I do. – old_timer May 07 '10 at 13:42