In the Intel x64 manual it says that there's XMM registers 0-7 in 32-bit SSE2 mode. Why then do 95% of the instructions that use these registers skip 0 and use 1-4?
For example, Intel's vol.2 manual entry for addps lists it as ADDPS xmm1, xmm2/m128.
You are misunderstanding something, probably the placeholders in the manual. When an instruction description says xmm1 or xmm2 it usually means any xmm register, the number just indicates operand numbering.
For example, ADDPS xmm1, xmm2/m128 can add two arbitrary xmm registers or add a memory operand to an arbitrary xmm register.
The numbering in Intel's manuals are placeholders, like first xmm operand, not register numbers.
Look at blendvps for one case where XMM0 is the only choice for one operand, not a placeholder, for the non-AVX version: https://felixcloutier.com/x86/blendvps.
| Opcode | Instruction | Op/En |
|---|---|---|
66 0F 38 14 /r |
BLENDVPS xmm1, xmm2/m128, <XMM0> |
RM0 |
VEX.128.66.0F3A.W0 4A /r /is4 |
VBLENDVPS xmm1, xmm2, xmm3/m128, xmm4 |
RVMR |
VEX.256.66.0F3A.W0 4A /r /is4 |
VBLENDVPS ymm1, ymm2, ymm3/m256, ymm4 |
RVMR |
Notice the all-caps <XMM0> inside angle brackets: That's what Intel writes when they mean a specific register is required. (Used implicitly in the machine code, like RDX:RAX for mul rcx)
Also notice the Op/En (Operand Encoding) column, which has a key for the other table, "Instruction Operand Encoding", where we can see the registers encoded by ModR/M (or VEX) fields, or even an immediate; vblendvps is kinda crazy. But anyway, given that there are bits in the instruction to encode them, it's clear they can be any XMM register.
| Op/En | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
|---|---|---|---|---|
| RM0 | ModRM:reg (r, w) | ModRM:r/m (r) | implicit XMM0 | NA |
| RVMR | ModRM:reg (w) | VEX.vvvv (r) | ModRM:r/m (r) | imm8[7:4] |
The (r,w) vs. (w) or (r) tells you whether an operand is read, written, or both.
See also
Or read the earlier chapter of vol.2 that tells you how to read the entries: The operand-encoding table has the details of exactly how an instruction specifies registers. How to read the Intel Opcode notation notation has an answer quoting some of it, but the actual PDF has examples and stuff.