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Waveform link included I have a confusion regarding the value assignment to signal in VHDL.

Confusion is that I have read that values to signal gets assigned at end of process.

  1. Does the value get assigned right when the process finishes or when the process is triggered the next time?

  2. If it is assigned at the end of the process then consider this scenario (3 flip flops in series i.e output of one flip flop is input to another) then if D1 is 1 at time 0 will not the output Q3 be 1 at the same time?

Curious
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    possible duplicate of [How does signal assignment work in a process?](http://stackoverflow.com/questions/5060635/how-does-signal-assignment-work-in-a-process) – Morten Zilmer May 05 '14 at 19:19
  • Your example for 2. is what happens with a chain of transparent latches. Flip-flops only update on an edge and will see the old value of whatever is driving their Q input not the new value it is updating to after the clock. In real systems you could introduce enough skew between clocks to cause this sort of fall through but it is not normally done in synchronous design. The VHDL simulation kernel ensures this won't happen unless you explicitly make it that way. – Kevin Thibedeau May 05 '14 at 21:48
  • Thank you for the quick response. My professor said that in VHDL on the rising edge clk event when a signal is assigned a register is formed. process(clk) if(clk='1' and clk'event)then output<=D; end if; ( what i understand from this is that on the rising edge the signal output is assigned to D but since it results into a register the signal output value will change on next rising clk edge(regsiter) is this right?? – Curious May 06 '14 at 16:06

2 Answers2

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(1) Right when the process finishes. More precisely, right after this and ALL processes running alongside this process have finished, and before any processes are subsequently started. So when any signal assignment happens, no process is running.

(2) Q3 will become the value on D1 three clock cycles earlier. Whether that value was '1' or not I can't tell from your question!

  • I have added the waveform link to the question. My professor said that in VHDL on the rising edge clk event when a signal is assigned a register is formed. process(clk) if(clk='1' and clk'event)then output<=D; end if; ( what i understand from this is that on the rising edge the signal output is assigned to D but since it results into a register the signal output value will change on next rising clk edge(regsiter) is this right?? Which output(1,2,3) will be correct in the link of the image?? – Curious May 06 '14 at 17:15
  • Which output do you expect? –  May 06 '14 at 19:03
  • I think since a register will be formed it will cause a delay in the output and thus the answer should be the one i showed in (output 1) in the image link. – Curious May 06 '14 at 19:12
  • No, a single register would be loaded on the next rising_edge(clk) after D, and its output would be immediately available : waveform 2. You would need a second register with its D connected to the first Q, both clocked from `clk` to get waveform 1. Try these in a simulator. –  May 06 '14 at 19:23
  • library ieee; use ieee.std_logic_1164.all; entity reg is generic ( width : positive := 8); port ( clk : in std_logic; rst : in std_logic; input : in std_logic_vector(width-1 downto 0); output : out std_logic_vector(width-1 downto 0)); end reg; architecture SYNC_RST of reg is begin if (clk'event and clk='1') then if (rst = '1') then output <= (others => '0'); else output <= input; end if; end if; end process; end SYNC_RST; --output->[link](https://www.dropbox.com/s/4gv2oo2q408n8lh/waveform.png) – Curious May 06 '14 at 20:13
  • I used the above code and got a delay of 1 cycle. The new values are assigned on the rising edge of clock.( is that the reason why i get output on the next clock edge here) [link](https://www.dropbox.com/s/6gzrbdfr93llq62/reg_tb.c) – Curious May 06 '14 at 22:04
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The signal assignment is done only at the end of the process. After signal assignment, there may exist signal updates and because of the signal updates, the process itself or maybe other processes which are sensitive to some of the updated signals will be triggered. This is the concept of delta-cycle. It happens in a zero simulation time. signal updates -> triggers process->at the end of the process, signals are updated ----------------------------------- ----------------------------------- this is one delta cycle starting of the second delta cycle

when there will be no signal update, the process finishes and the the simulation time increments.

user3690624
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